Add more WIP panels to pedestal

Signed-off-by: fly <merspieler@alwaysdata.com>
This commit is contained in:
fly 2024-04-17 12:55:01 +02:00
parent 10ae7bf917
commit 7091862561
35 changed files with 50728 additions and 0 deletions

3
.gitmodules vendored
View file

@ -4,3 +4,6 @@
[submodule "Pedestal/111VU-Flood-Integ-Light/pcb/NiasStuff.pretty"] [submodule "Pedestal/111VU-Flood-Integ-Light/pcb/NiasStuff.pretty"]
path = Pedestal/111VU-Flood-Integ-Light/pcb/NiasStuff.pretty path = Pedestal/111VU-Flood-Integ-Light/pcb/NiasStuff.pretty
url = https://git.merspieler.tk/fly/NiasStuff-kicad.git url = https://git.merspieler.tk/fly/NiasStuff-kicad.git
[submodule "Pedestal/PedestalConnectBox/pcb/NiasStuff.pretty"]
path = Pedestal/PedestalConnectBox/pcb/NiasStuff.pretty
url = https://git.merspieler.tk/fly/NiasStuff-kicad.git

File diff suppressed because it is too large Load diff

View file

@ -0,0 +1,77 @@
{
"board": {
"active_layer": 0,
"active_layer_preset": "",
"auto_track_width": true,
"hidden_netclasses": [],
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"images": 0.6,
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
},
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": false,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
},
"visible_items": [
0,
1,
2,
3,
4,
5,
8,
9,
10,
11,
12,
13,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
32,
33,
34,
35,
36,
39,
40
],
"visible_layers": "ffcffff_ffffffff",
"zone_display_mode": 0
},
"meta": {
"filename": "109VU.kicad_prl",
"version": 3
},
"project": {
"files": []
}
}

View file

@ -0,0 +1,497 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.09999999999999999,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.15,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.762,
"height": 1.524,
"width": 1.524
},
"silk_line_width": 0.15,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"min_clearance": 0.35
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "warning",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rules": {
"max_error": 0.005,
"min_clearance": 0.127,
"min_connection": 0.127,
"min_copper_edge_clearance": 0.254,
"min_hole_clearance": 0.254,
"min_hole_to_hole": 0.09999999999999999,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 1,
"min_silk_clearance": 0.0,
"min_text_height": 0.7,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.19999999999999998,
"min_track_width": 0.127,
"min_via_annular_width": 0.09999999999999999,
"min_via_diameter": 0.5,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0,
0.127,
0.2,
0.6
],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
},
{
"diameter": 0.5,
"drill": 0.3
}
],
"zones_allow_external_fillets": false
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "ignore",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "109VU.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
}
],
"meta": {
"version": 3
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"page_layout_descr_file": "",
"plot_directory": "",
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"6febedca-6a53-46b7-8fb5-6d0e2569137f",
""
]
],
"text_variables": {}
}

File diff suppressed because it is too large Load diff

View file

@ -0,0 +1,10 @@
*.swp
*.swo
~*
_autosave*
fp-info-cache
*-backups
\#auto_saved_files#
*.blend
*.blend1
*.mtl

File diff suppressed because one or more lines are too long

View file

@ -0,0 +1,99 @@
(footprint "Potentiometer_Alps_RK09L_Double_Vertical" (version 20221018) (generator pcbnew)
(layer "F.Cu")
(descr "1240015 1240019 12D0A1W 12D0A1T Potentiometer, vertical, Alps RK09L Double, https://tech.alpsalpine.com/prod/e/pdf/potentiometer/rotarypotentiometers/rk09l/rk09l.pdf")
(tags "Potentiometer vertical Alps RK09L Double")
(attr through_hole)
(fp_text reference "REF**" (at 6.975 -5.5) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 3ad2cce2-a52c-44db-bb6d-df323928ecd7)
)
(fp_text value "Potentiometer_Alps_RK09L_Double_Vertical" (at 6.975 10.5) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp a183882f-856d-4ac6-8f9b-237402a49391)
)
(fp_text user "${REFERENCE}" (at 4.5 2.5 90) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 1dfea68d-d863-44b4-84c2-631b1c630b5c)
)
(fp_line (start 3.38 -3.67) (end 3.38 -0.871)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 5b19cfcf-74d9-4800-82ef-58b8c8dcd158))
(fp_line (start 3.38 -3.67) (end 8.046 -3.67)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 9638be89-1182-494c-b34a-cef6c65aa73f))
(fp_line (start 3.38 0.871) (end 3.38 1.63)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 1289c580-433d-4211-89c2-350befc86fb3))
(fp_line (start 3.38 3.371) (end 3.38 4.13)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 8b4d016a-c57e-4600-928f-676f641ab47b))
(fp_line (start 3.38 5.87) (end 3.38 8.67)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp a2b095fa-8f80-4d09-ac86-5b519aedf6b6))
(fp_line (start 3.38 8.67) (end 8.046 8.67)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 823c7b67-db49-4c69-9711-73a4e94682bf))
(fp_line (start 11.955 -3.67) (end 14.97 -3.67)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 0ba14c84-7d30-4862-b71e-8f90841eed02))
(fp_line (start 11.955 8.67) (end 14.97 8.67)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 35a818be-6a48-476d-bd45-5a59e1cd58ca))
(fp_line (start 14.97 -3.67) (end 14.97 8.67)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp e6f8ef56-a270-4378-85be-878dc06d0ac1))
(fp_rect (start 5 0.5) (end 6.5 4.5)
(stroke (width 0.12) (type solid)) (fill none) (layer "F.SilkS") (tstamp f415282e-f854-4428-afb8-0000af146061))
(fp_rect (start 13.5 0.5) (end 15 4.5)
(stroke (width 0.12) (type solid)) (fill none) (layer "F.SilkS") (tstamp 437aaa5a-67f2-4a09-b716-1136ca096c4c))
(fp_line (start -1.15 -4.5) (end -1.15 9.5)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 8896f315-99c2-4161-83b1-89445ff97182))
(fp_line (start -1.15 9.5) (end 15.1 9.5)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 4ce66855-9d36-4e40-93e9-07afe7cad46d))
(fp_line (start 15.1 -4.5) (end -1.15 -4.5)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 34dee3c7-e8cf-4b40-8f8f-ddbfcabd24c9))
(fp_line (start 15.1 9.5) (end 15.1 -4.5)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp e0c59b95-11a1-4057-84de-ec4662ccf454))
(fp_line (start 3.5 -3.55) (end 3.5 8.55)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp d733fd62-89eb-4093-8b3a-9da14d9cb929))
(fp_line (start 3.5 8.55) (end 14.85 8.55)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 3d847fa4-4158-4f94-9cb4-14c46a8a131b))
(fp_line (start 14.85 -3.55) (end 3.5 -3.55)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 1568dbf4-80ae-4b2e-bf29-0a58bf159bac))
(fp_line (start 14.85 8.55) (end 14.85 -3.55)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp d9db4b91-2c18-4025-93f7-e34d44372fce))
(fp_circle (center 10 2.5) (end 13 2.5)
(stroke (width 0.1) (type solid)) (fill none) (layer "F.Fab") (tstamp abd3e247-ec9f-408d-bd54-37282c07d6ec))
(pad "1" thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (tstamp 99a05ca1-d969-45e2-86c4-d34da3051abd))
(pad "2" thru_hole circle (at 0 2.5) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (tstamp 3bac6dfa-d7fe-489b-a1a7-7651495fe7fa))
(pad "3" thru_hole circle (at 0 5) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (tstamp 0e561606-b992-42c4-aef5-458a512f6b6b))
(pad "4" thru_hole circle (at 2.5 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (tstamp 43fb1ad0-b982-4374-be37-b53c9d5c6c69))
(pad "5" thru_hole circle (at 2.5 2.5) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (tstamp 2db468ce-74b6-4b8e-be3b-d954e0a4d82c))
(pad "6" thru_hole circle (at 2.5 5) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (tstamp 84f455f6-0e54-4bd9-8a21-565c54e63408))
(pad "MP" thru_hole roundrect (at 10 -2.25) (size 2 3) (drill oval 1.1 1.8) (layers "*.Cu" "*.Mask") (roundrect_rratio 0.25) (tstamp 60dd39b8-21f5-4094-b0e8-eb7921a73060))
(pad "MP" thru_hole roundrect (at 10 7.25) (size 2 3) (drill oval 1.1 1.8) (layers "*.Cu" "*.Mask") (roundrect_rratio 0.25) (tstamp 7e50628f-299a-426c-9253-e9120f8f7413))
(zone (net 0) (net_name "") (layer "F.Cu") (tstamp db4b3fd7-8808-4be0-88b9-faa4d762c095) (name "Copper Keep Out") (hatch full 0.508)
(connect_pads (clearance 0))
(min_thickness 0.254) (filled_areas_thickness no)
(keepout (tracks not_allowed) (vias not_allowed) (pads not_allowed) (copperpour not_allowed) (footprints not_allowed))
(fill (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
(xy 6.5 4.5)
(xy 5 4.5)
(xy 5 0.5)
(xy 6.5 0.5)
)
)
)
(zone (net 0) (net_name "") (layer "F.Cu") (tstamp 1399f001-fcc8-44ad-93cd-45f556537d9b) (name "Copper Keep Out") (hatch full 0.508)
(connect_pads (clearance 0))
(min_thickness 0.254) (filled_areas_thickness no)
(keepout (tracks not_allowed) (vias not_allowed) (pads not_allowed) (copperpour not_allowed) (footprints not_allowed))
(fill (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
(xy 14.9 4.5)
(xy 13.5 4.5)
(xy 13.5 0.5)
(xy 14.9 0.5)
)
)
)
(model "${KIPRJMOD}/NiasStuff.pretty/RK09L_Double_Vertical.x3d"
(offset (xyz 10.25 -2.5 -18))
(scale (xyz 0.4 0.4 0.4))
(rotate (xyz 0 180 90))
)
)

File diff suppressed because one or more lines are too long

File diff suppressed because one or more lines are too long

View file

@ -0,0 +1,32 @@
(footprint "SW_SPDT_YUEN-FUNG_ST-0-103-A01-T000-RS" (version 20221018) (generator pcbnew)
(layer "F.Cu")
(attr through_hole)
(fp_text reference "REF**" (at 0 -3.3 unlocked) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.1)))
(tstamp b3347772-b2bc-4dd2-b1d6-ab507c7be330)
)
(fp_text value "SW_SPDT_YUEN-FUNG_ST-0-103-A01-T000-RS" (at 0 1 unlocked) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 196fef8f-cdec-4adc-81cf-f5d7c6df064b)
)
(fp_text user "${REFERENCE}" (at 0 2.5 unlocked) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 2c8a2d74-6e90-4060-b12c-154ea5f3f567)
)
(fp_line (start -4.15 -2.6) (end 4.15 -2.6)
(stroke (width 0.05) (type default)) (layer "F.CrtYd") (tstamp 1d2098e2-93cb-4587-8e50-8b07f509ff17))
(fp_line (start -4.15 2.6) (end -4.15 -2.6)
(stroke (width 0.05) (type default)) (layer "F.CrtYd") (tstamp aebd1803-2a65-4b7f-b52d-0168ae5025c2))
(fp_line (start 4.15 -2.6) (end 4.15 2.6)
(stroke (width 0.05) (type default)) (layer "F.CrtYd") (tstamp f3b79f61-3b7b-473c-bf7d-3a1776a28928))
(fp_line (start 4.15 2.6) (end -4.15 2.6)
(stroke (width 0.05) (type default)) (layer "F.CrtYd") (tstamp dd6daa8e-5a8a-4abe-abb0-4ae00fb6f47b))
(pad "1" thru_hole oval (at -2.54 0) (size 1.524 2.3) (drill oval 0.6 1.5) (layers "*.Cu" "*.Mask") (tstamp a841b6d6-ce93-49b4-8c76-4472cad9e42e))
(pad "2" thru_hole oval (at 0 0) (size 1.524 2.3) (drill oval 0.6 1.5) (layers "*.Cu" "*.Mask") (tstamp b71860ad-88ba-47ab-8465-9afda6f4e407))
(pad "3" thru_hole oval (at 2.54 0) (size 1.524 2.3) (drill oval 0.6 1.5) (layers "*.Cu" "*.Mask") (tstamp de7d9fe5-4bd4-4c3b-9607-46733355f24e))
(model "${KIPRJMOD}/NiasStuff.pretty/ST-0-103-A01-T000-RS.x3d"
(offset (xyz 0 0 0))
(scale (xyz 0.2 0.2 0.2))
(rotate (xyz 180 0 0))
)
)

View file

@ -0,0 +1,71 @@
(footprint "USB_C_Receptacle_G-Switch_GT-USB-7010ASV" (version 20221018) (generator pcbnew)
(layer "F.Cu")
(descr "USB Type C, right-angle, SMT, https://datasheet.lcsc.com/lcsc/2204071530_G-Switch-GT-USB-7010ASV_C2988369.pdf")
(tags "USB C Type-C Receptacle SMD")
(attr smd)
(fp_text reference "REF**" (at 0 -5.5) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp a432b3eb-92f8-4746-aff4-7ac94a8dcf05)
)
(fp_text value "USB_C_Receptacle_G-Switch_GT-USB-7010ASV" (at 0 5) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp cd301a04-be52-4bc1-963f-69790b266d55)
)
(fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 15ef0862-0895-4acd-966d-bd9a9754a23f)
)
(fp_line (start -4.58 -1.85) (end -4.58 0.07)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 7333808c-2e1b-4f52-a96e-0b8bb198f20f))
(fp_line (start -4.58 3.785) (end -4.58 2.08)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 4dfe202d-491c-4175-92c2-29c1fd23f31e))
(fp_line (start 4.58 0.07) (end 4.58 -1.85)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 848ce5ad-983a-4d40-871a-7c4fc602e9b5))
(fp_line (start 4.58 2.08) (end 4.58 3.785)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 6c015a9e-1a65-4d00-b36a-7395b6b9a2df))
(fp_line (start 4.58 3.785) (end -4.58 3.785)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 33e31502-05f6-4138-872e-a793a51b52d0))
(fp_line (start -5.32 -4.85) (end 5.32 -4.85)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 9e051379-7f1d-44d0-9345-a45543d447e4))
(fp_line (start -5.32 4.18) (end -5.32 -4.85)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 9c0bbfdb-3dc7-499b-aefe-cd1509d72229))
(fp_line (start 5.32 -4.85) (end 5.32 4.18)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 553101a2-df2e-4179-a908-8c17b467f5f1))
(fp_line (start 5.32 4.18) (end -5.32 4.18)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp b99dad18-feeb-4adb-ab5a-250a9fcc99b2))
(fp_line (start -4.47 -3.675) (end -4.47 3.675)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp feaad850-cb66-476a-9576-8d89ea758d13))
(fp_line (start -4.47 -3.675) (end 4.47 -3.675)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 198bdb9f-be8d-4f3f-bfec-8103a1805610))
(fp_line (start -4.47 3.675) (end 4.47 3.675)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp bd4bb27b-34af-460f-a05c-3423e8a6f16a))
(fp_line (start 4.47 3.675) (end 4.47 -3.675)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 4c7867ff-4861-413a-95ed-6aa3c62cbae6))
(pad "" np_thru_hole circle (at -2.89 -2.605) (size 0.65 0.65) (drill 0.65) (layers "*.Cu" "*.Mask") (tstamp e5754d6e-8009-4def-9ca7-318b44aee975))
(pad "" np_thru_hole circle (at 2.89 -2.605) (size 0.65 0.65) (drill 0.65) (layers "*.Cu" "*.Mask") (tstamp ffb3c201-5fd3-42bd-9f52-b57c734e38f5))
(pad "A1" smd rect (at -3.2 -3.725) (size 0.6 1.24) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp dac84c22-f52c-4778-928e-2bcaa3760910))
(pad "A4" smd rect (at -2.4 -3.725) (size 0.6 1.24) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp ba3fd611-10c5-4268-abc5-3fb10032940e))
(pad "A5" smd rect (at -1.25 -3.725) (size 0.3 1.24) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 043253ec-169a-406e-ac54-04e7a03006c2))
(pad "A6" smd rect (at -0.25 -3.725) (size 0.3 1.24) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 47861ba2-45a3-46b7-8842-f8b8f3640795))
(pad "A7" smd rect (at 0.25 -3.725) (size 0.3 1.24) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 79c119c7-9796-4e8f-9318-714374272823))
(pad "A8" smd rect (at 1.25 -3.725) (size 0.3 1.24) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 6e946a96-5b3b-4ce4-829e-d7e15ee1eb71))
(pad "A9" smd rect (at 2.4 -3.725) (size 0.6 1.24) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp acca73e5-e87c-4060-9cbb-3dc0ccb17db3))
(pad "A12" smd rect (at 3.2 -3.725) (size 0.6 1.24) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp b31575f1-9e38-4318-b460-fba61cc3ad31))
(pad "B1" smd rect (at 3.2 -3.725) (size 0.6 1.24) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 5f5b9b6b-9c93-4caa-b4ca-534482087cfc))
(pad "B4" smd rect (at 2.4 -3.725) (size 0.6 1.24) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 5f8cf630-1181-4dd6-987b-644ac7435976))
(pad "B5" smd rect (at 1.75 -3.725) (size 0.3 1.24) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 32c76394-9ef1-4442-862a-c2ccb40f3e44))
(pad "B6" smd rect (at 0.75 -3.725) (size 0.3 1.24) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 6ff83b81-c7ed-4a4a-b9f5-b5a04c3e32cd))
(pad "B7" smd rect (at -0.75 -3.725) (size 0.3 1.24) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 77be9aa8-9d59-48f6-a32b-7f234368fc3d))
(pad "B8" smd rect (at -1.75 -3.725) (size 0.3 1.24) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 665cf146-749f-4b35-810c-c2d1c2d23ad6))
(pad "B9" smd rect (at -2.4 -3.725) (size 0.6 1.24) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 552311fe-2027-4dd7-8283-67de72ec71b5))
(pad "B12" smd rect (at -3.2 -3.725) (size 0.6 1.24) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp ff3638ab-f24f-4337-9e29-4cb413c5f8d4))
(pad "S1" thru_hole oval (at -4.32 -3.125) (size 1 2.1) (drill oval 0.6 1.7) (layers "*.Cu" "*.Mask") (tstamp 349b922c-4b57-4a5a-b9e9-fbd2200ecc79))
(pad "S1" thru_hole oval (at -4.32 1.075) (size 1 1.8) (drill oval 0.6 1.4) (layers "*.Cu" "*.Mask") (tstamp 30e55750-5283-490a-8687-4be74b145ce7))
(pad "S1" thru_hole oval (at 4.32 -3.125) (size 1 2.1) (drill oval 0.6 1.7) (layers "*.Cu" "*.Mask") (tstamp 86ef7f00-b092-47ac-8a4a-9d36df529db6))
(pad "S1" thru_hole oval (at 4.32 1.075) (size 1 1.8) (drill oval 0.6 1.4) (layers "*.Cu" "*.Mask") (tstamp 9384f131-71cb-498f-9829-60301a016f43))
(model "${KIPRJMOD}/NiasStuff.pretty/GT-USB-7010C.x3d"
(offset (xyz 0 0 0))
(scale (xyz 0.4 0.4 0.4))
(rotate (xyz 180 0 180))
)
)

View file

@ -0,0 +1,4 @@
(fp_lib_table
(version 7)
(lib (name "NiasStuff")(type "KiCad")(uri "${KIPRJMOD}/NiasStuff.pretty")(options "")(descr ""))
)

View file

@ -0,0 +1,18 @@
Assuming origin being bottom left
Units: mm
Multiscan (2pos switch) axis at: x: 56.5 y: 54
CCS (2pos switch) axis at: x: 88.5 y: 54
Gain (pot) axis at: x: 31.5 y: 38
Tilt (pot) axis at: x: 113.5 y: 38
Mode (rot enc) axis at: x: 72.5 y: 19
SYS (3 pos switch) axis at: x: 44.5 y: 14
PWS (2 pos switch) axis at: x: 100 y: 14
Theoretical max dimensions (not accounting for case size):
x: 65
y: 140
Current grid origin: x: 65 y: 140

Binary file not shown.

After

Width:  |  Height:  |  Size: 235 KiB

View file

@ -0,0 +1,2 @@
(kicad_pcb (version 20221018) (generator pcbnew)
)

View file

@ -0,0 +1,77 @@
{
"board": {
"active_layer": 0,
"active_layer_preset": "",
"auto_track_width": true,
"hidden_netclasses": [],
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"images": 0.6,
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
},
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": false,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
},
"visible_items": [
0,
1,
2,
3,
4,
5,
8,
9,
10,
11,
12,
13,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
32,
33,
34,
35,
36,
39,
40
],
"visible_layers": "fffffff_ffffffff",
"zone_display_mode": 0
},
"meta": {
"filename": "112VU.kicad_prl",
"version": 3
},
"project": {
"files": []
}
}

View file

@ -0,0 +1,332 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.1,
"copper_line_width": 0.2,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"other_line_width": 0.15,
"silk_line_width": 0.15,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"rules": {
"min_copper_edge_clearance": 0.0,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0
},
"track_widths": [],
"via_dimensions": []
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "ignore",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "112VU.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
}
],
"meta": {
"version": 3
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"page_layout_descr_file": "",
"plot_directory": "",
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"b008bd47-fb76-4bc5-bf5f-6d0fcbf0f1f4",
""
]
],
"text_variables": {}
}

File diff suppressed because it is too large Load diff

View file

@ -0,0 +1,2 @@
(kicad_pcb (version 20221018) (generator pcbnew)
)

View file

@ -0,0 +1,77 @@
{
"board": {
"active_layer": 0,
"active_layer_preset": "",
"auto_track_width": true,
"hidden_netclasses": [],
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"images": 0.6,
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
},
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": false,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
},
"visible_items": [
0,
1,
2,
3,
4,
5,
8,
9,
10,
11,
12,
13,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
32,
33,
34,
35,
36,
39,
40
],
"visible_layers": "fffffff_ffffffff",
"zone_display_mode": 0
},
"meta": {
"filename": "119VU.kicad_prl",
"version": 3
},
"project": {
"files": []
}
}

View file

@ -0,0 +1,332 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.1,
"copper_line_width": 0.2,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"other_line_width": 0.15,
"silk_line_width": 0.15,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"rules": {
"min_copper_edge_clearance": 0.0,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0
},
"track_widths": [],
"via_dimensions": []
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "ignore",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "119VU.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
}
],
"meta": {
"version": 3
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"page_layout_descr_file": "",
"plot_directory": "",
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"b6b7e20a-d4fe-4b2b-94b3-5922c66ef010",
""
]
],
"text_variables": {}
}

File diff suppressed because it is too large Load diff

View file

@ -0,0 +1,2 @@
(kicad_pcb (version 20221018) (generator pcbnew)
)

View file

@ -0,0 +1,77 @@
{
"board": {
"active_layer": 0,
"active_layer_preset": "",
"auto_track_width": true,
"hidden_netclasses": [],
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"images": 0.6,
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
},
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": false,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
},
"visible_items": [
0,
1,
2,
3,
4,
5,
8,
9,
10,
11,
12,
13,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
32,
33,
34,
35,
36,
39,
40
],
"visible_layers": "fffffff_ffffffff",
"zone_display_mode": 0
},
"meta": {
"filename": "8VU.kicad_prl",
"version": 3
},
"project": {
"files": []
}
}

View file

@ -0,0 +1,332 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.1,
"copper_line_width": 0.2,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"other_line_width": 0.15,
"silk_line_width": 0.15,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"rules": {
"min_copper_edge_clearance": 0.0,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0
},
"track_widths": [],
"via_dimensions": []
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "ignore",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "8VU.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
}
],
"meta": {
"version": 3
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"page_layout_descr_file": "",
"plot_directory": "",
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"24af7b7a-e4a0-4247-9a6e-9f7942f7a65d",
""
]
],
"text_variables": {}
}

File diff suppressed because it is too large Load diff

@ -0,0 +1 @@
Subproject commit 42895cef104041cf2af13b8863f5a334a8a22bd4

View file

@ -0,0 +1,2 @@
(kicad_pcb (version 20221018) (generator pcbnew)
)

View file

@ -0,0 +1,77 @@
{
"board": {
"active_layer": 0,
"active_layer_preset": "",
"auto_track_width": true,
"hidden_netclasses": [],
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"images": 0.6,
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
},
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": false,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
},
"visible_items": [
0,
1,
2,
3,
4,
5,
8,
9,
10,
11,
12,
13,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
32,
33,
34,
35,
36,
39,
40
],
"visible_layers": "fffffff_ffffffff",
"zone_display_mode": 0
},
"meta": {
"filename": "PedestalConnectBox.kicad_prl",
"version": 3
},
"project": {
"files": []
}
}

View file

@ -0,0 +1,336 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.1,
"copper_line_width": 0.2,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"other_line_width": 0.15,
"silk_line_width": 0.15,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"rules": {
"min_copper_edge_clearance": 0.0,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0
},
"track_widths": [],
"via_dimensions": []
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "ignore",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "PedestalConnectBox.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
}
],
"meta": {
"version": 3
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"page_layout_descr_file": "",
"plot_directory": "",
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"a2f8714b-93e7-42e9-99f5-bed65093f325",
""
],
[
"98b768ad-78b8-419f-8ce6-c0590b9bbfd7",
"Power & USB"
]
],
"text_variables": {}
}

File diff suppressed because it is too large Load diff

View file

@ -0,0 +1,4 @@
(fp_lib_table
(version 7)
(lib (name "NiasStuff")(type "KiCad")(uri "${KIPRJMOD}/NiasStuff.pretty")(options "")(descr ""))
)

File diff suppressed because it is too large Load diff

BIN
common-3d/knob2.stl Normal file

Binary file not shown.